FIG. 1 is a cross-section view for part of an intermetal dielectric structure 20 of a semiconductor device from the prior art. In FIG. 1, a conductive line 22 is underlying a dielectric layer 24. The conductive line 22 is formed in another dielectric layer (not shown in this view). The dielectric layer 24 in the example structure 20 shown in FIG. 1 includes a capped layer 26, which serves as a diffusion barrier and/or etch stop, and a layer of insulating material 28. A via 30 is formed in the dielectric layer 24 and opens to the conductive line 22. The capped layer 26 helps to control diffusion of underlying conductive lines and the etching of the via 30. A top portion of the via 30 may open to another conductive line (not shown in FIG. 1), for example, such as in a dual damascene structure. The via 30 of FIG. 1 is lined with a barrier layer 32 (e.g., Ta or TaN) and then filled with a conducting material 34 (e.g., copper). Hence, the conducting material 34 in the via is electrically connected to the underlying conductive line 22 through the bottom of the via 30 and through the barrier layer 32. Under ideal conditions for forming this structure 20 shown in FIG. 1, the bottom of the via 30 completely opens to the conductive line 22. During actual processing, however, the via 30 may only partially open to the underlying conductive line 22, as shown in FIG. 2.
In the case shown in FIG. 2, part of the capped layer 26 remains between the barrier layer 32 and the conductive line 22. This will likely increase the resistance between the conducting material 34 in the via 30 and the conductive line 22, which is typically undesirable. In an even worse case, the via 30 may not open to the conductive line 22 at all, as shown in FIG. 3. Thus in FIG. 3, the conducting material 34 may not be electrically connected to the conductive line 22 because the barrier layer 32 is not physically contacting the conductive line 22 and is separated from the conductive line 22 by a thin portion of the capped layer 26, which should have been etched away. In such case, a capacitor may be formed at the bottom of the via 30, which may be highly undesirable (e.g., when an low resistance electrical connection was desired). Such problems illustrated in FIGS. 2 and 3 may lead to higher resistance at the via and/or unstable yield and/or decreased reliability. Hence, there is a need for an improved via structure providing less resistance on average, more stable yields, and improved processing reliability.